Monolithic integrated structure including fabrication and package therefor

ABSTRACT

A monolithic integrated semiconductor structure is described that has a plurality of functionally isolated individual cells that are electrically interconnected. Each of the cells is an object or mirror image cell that is vertically, horizontally and diagonally displaced from the object cell. The plurality of cells provide a memory array with electrical components of each memory cell composed of active and passive semiconductor devices. Other important aspects of the structure include underpass connections and active devices in a common portion of the structure which are electrically interconnected at the same node potential by means of a highly doped buried region within the common portion of the structure. In particular, a sophisticated packaging scheme for containing such a highly complex array of memory cells is disclosed.

United States Patent 1191 Wegner et a1. 317/234 Agusta et al. July 9, 1974 [54] MONOLITHIC INTEGRATED STRUC I IVIRE 3,508,118 4/1978 alellirin et al 317/101 3,512,051 5 197 o 317/234 FABRICATION AND PACKAGE 3,547,604 12/1970 Davis et al. 29/577 [755] Memo: 2:??? f gfl Ba'deh; Primary Examiner-Rudolph v. Rolinec g fit Hen] Assistant ExaminerE. Wojciechowicz Hy Par}? Raymond P g Attorney, Agent, or Firm-Theodore E. Galanthay Poughkeepsie, all of NY. [73] Assignee: International Business Machines [57] ABSTRACT Corporanon, Armonk, A monolithic integrated semiconductor structure is [22] Filed; AP 16, 1970 1 described that has a plurality of functionally isolated individual cells that are electrically interconnected. pp N05 33,119 Each of the cells is an object or mirror image cell that Related US Application Data is vertically horizontally and diagonally displaced [62] Division of Ser No 539 210 March 31 1966 Pat from the Object h The Pluralhy of cehs Provide a No 3 508 209 memory array with electrical components of each memory cell composedof active and passive semicon- U S R 3 M N dUCtOI' devices. Other important aspects Of the SU'UC- 174/56 ture include underpass connections and active devices [51] Int. Cl. .Q H011 5/00 in a Common portion of the Structure which are elec [58] Field of a a; I 317/23'4 5 3 5 trically interconnected at the same node potential by 4 id means of a highly doped buried region within the common portion of the structure. In particular, a sophisti [56] References Cited cated packaging scheme for containing such a highly UNITED STATES PATENTS complex array of memory cells is disclosed. 3,195.026 7/1965 3 Claims, 40 Drawing Figures PATENTED 4 3.823.348

sum 01 or 23 F I G. I

'I T FORM SEMICONDUCTOR WAFER REOXIDIZE WAFER FORM NETAI- INTERCONNEC- OF P TYPE CONDUCTIVITY SURFACE TIONS AND OHMIC CONTACTS OXIOIZE WAFER SURFACE MASK AND ETCH HOLES IN OXIDE LAYER ABOVE EPITAXIALLY GROWN REGIONS APPLY SPUTTEREO OXIDE OVERCOAT MASK AND ETCH HOLES IN OXIDE LAYER DIFFUSE P TYPE BASE,

DIODE,AND RESISTOR REGIONSINTO ISOLATED EPITAXIALLY GROWN REGIONS MASX AND ETCH TERMINAL HOLES IN SPUTTERED OXIDE OVERCOAT LAYER FORM N REGIONS IN THE WAFER SURFACE BY DIFFUSION OXIOIZE WAFER SURFACE TO CREATE DEPRESSION ABOVE N REGIONS OXIOIZE SURFACE AND DRIVE IN IMPURITIES FORMING THE BASE,DIODE,AND RESISTOR REGIONS REMOVE OXIDE LAYER MASK AND ETCH HOLES IN OXIDE LAYER ABOVE BASE REGIONS EPITAXIALLY GROW A LAYER OF N TYPE MATERIAL ON THE WAFER SURFACE AND ON THE N* REGION DIFFUSE IN N TYPE IMPU- RITIES TO FORM EMITTER REGIONS WITHIN THE BASE REGIONS OXIOIZE SURFACE OF OXIOIZE SURFACE AND DRIVE IN IMPURITIES FORMING THE EMITTER REGION EPITAXIALLY CROWN LAYER MASII AND ETCH A NETWORK OF CHANNELS IN THE OXIDE LAYER EXPOSINC THE SEMI- CONDUCTOR SURFACE EVAPORATE GOLD ONTO EX- POSEO SEMICONDUCTOR SURFACE AND DIFFUSE GOLD INTO WAFER IN NONOXIDIZING ATMOSPHERE ANNEAL WAFER AND RECOVER OF TRANSISTOR DEVICES MASK AND ETCH HOLES IN OXIDE LAYER FOR FORMING CONTACTS TO DESIRED SEMI- CONDUCTOR REGIONS EVAPORATE CR, CU, AND AU INTO TERMINAL HOLES EVAPORATE OVERSIZE PB-SN PADS ONTO CR,CU,AU LAND PORTIONS MELT ms T0 REFLOVI BACK TO LANDS DICE WAFER INTO CHIPS I A APPLY MONOLITH INTEGRATED CHIPS ON PRIN- TED LAND PATTERNS ON CERAMIC SUBSTRATE INTERCONNECT MONOLITHIC INTEGRATED CHIPS TO PRINTED LAND PATTERN INVENTORS BENJAMIN AGUSTA PAUL H. BARDELL PAUL P. CASTRUCCI ROBERT A HENLE RAYMOND P. PECORARO BY ms? ATTORNEY PATENTEDJUL 9mm sum our 2 PATENTEB JUL 91514 sum D IOF 23 ACTIVE PASSIVE COMPLETE ALL DIFFUSION AND DEVICES oxmmou OPERATIONS EXCEPT A nouourmc SEMICONDUCTOR STRUCTURE FOR Hm DIFFUSION TO FORM FORM THE FINAL OXIDE LAYER ON THE SURFACE OF THE 7 MONOLITHIC SEMICONDUCTOR STRUCTURE REMOVE A SELECTED PORTION OF THE FINAL OXIDE LAYER TO EXPOSE A SURFACE PORTION OF THE SEMICONDUCTOR STRUCTURE I l I I PERFORM A NON- OXIOIZINC ANNEAL OPERATION TO INCREASE THE CURRENT CAIN OF THE ACTIVE DEVICES ACTIVE AND/ OR PASSIVE DEVICES IN A MONOLITHIC SEMICONDUCTOR STRUCTURE REMOVE A SELECTED PORTION OF THE FINAL OXIDE LAYER TO EXPOSE SEMICONDUCTOR SURFACE PERFORM FINAL DIFFUSION OPERATION TO FORM DESIRED SEMICONDUCTOR DEVICES YIITHOUT A FINAL OXIDATION STEP TOTAL CARRIER LIFETIME KILLER DIFFUSION TIME (INCLUDING FURNACE RECOVERY TIME) PATENTEDJUL 91914 3,823,348

sum as or 23 FIG.2

PATENTEU JUL 91914 SHEET 07 0F 23 PATENTED sum as or 2s JNQE PATENTEDJJ. 91974 sum as nr 23 DNdE PATENTEDJUL 91914 3.823.348

sum 10 or 23 FIG. 3

PATENTEIJ L 9 I974 SHEET 11 0F 23 FIG.4

I ICIIQ/ I J T ZII I GND VERTICAL PLANE HORIZONTAL PL E 0| NAL IMAGE OBJECTIWORDI MIRROR IMAGEIIWORDI MIRROR IMAGE (wo RD) FIG.I7AA

ASKS

PATENTED V 3,823,348 um 11 ur 21y .lT fgn A 1 i MASKD MASKC MASK E CR CU AU CHIP LAND MASK PB-SN PAD "As ,FIGJTV PB-SN PAD MASK CR-CU-AU CHIP LAND MASK PATENTEB JUL 91914 sum '1aor23 FIG. 19 

1. A monolithic integrated semiconductor structure comprising, in combination, a plurality of functionally isolated individual cells electrically interconnected, each of said cells comprising active and passive devices, one of said active devices comprises a diode and a transistor, said diode and transistor being located in a common portion of said monolithic semiconductor structure which is isolated from other said active and passive devices, said diode and transistor in said common portion of the structure being electrically interconnected at the same node potential by means of a highly doped buried region within said common portion of the structure, each of said cells is provided with external terminal connection regions electrically interconnected to said cells, each of said external connection regions comprising layers of chrome, copper, and gold electrically connected to a lead-tin pad.
 2. A monolithic integrated semiconductor structure in accordance with claim 1, in which an aluminum land pattern is provided for electrically interconnecting the selected terminal connection regiOns to each cell.
 3. A package for monolithic integrated memory arrays comprising, in combination: a dielectric substrate; a conductive land pattern formed on a surface of said dielectric substrate including terminal end portions; a plurality of pins penetrating said dielectric substrate and connected to selected terminal end portions; at least two monolithic integrated memory array chips spaced from the surface of said dielectric substrate and interconnected to said lands; each said monolithic integrated memory array chips being formed on a monocrystalline semiconductor substrate having terminal pads located about the peripheral portion of said monocrystalline semiconductor substrate, the terminal pads being formed in sets of substantially parallel lines thereby defining an area in said monocrystalline semiconductor substrate, each said area including a plurality of functionally isolated memory cells, each said cells having an electrical connection to a terminal pad each terminal pad comprising layers of chrome, copper and gold electrically connected to one of said conductive land patterns formed on the surface of said dielectric substrate. 